Dual work-function metal gates

ABSTRACT

A semiconductor device having dual work-function structures, such as dual work-function gate electrodes of transistors. In the preferred embodiment in which NMOS and PMOS transistors are formed on a semiconductor device, the transistors are initially formed with a dummy gate electrode and a dummy dielectric layer. The dummy gate electrode and dummy dielectric layers are removed. A gate dielectric layer and a first electrode layer are formed. A nitridation process is performed on the NMOS transistor to reduce the work function of the gate electrode. A second electrode layer is then formed on the first electrode layer.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, andmore particularly to dual work-function metal electrode gates for metaloxide semiconductor field-effect transistors (MOSFETs).

BACKGROUND

Complementary metal-oxide-semiconductor (CMOS) technology is thedominant semiconductor technology used for the manufacture ofultra-large scale integrated (ULSI) circuits today. Current CMOStransistors typically utilize polysilicon as the gate electrode for bothNMOS and PMOS transistors, wherein the polysilicon is doped with anN-type dopant to form NMOS transistors and is doped with a P-type dopantto form PMOS transistors. Polysilicon gates, however, often exhibit gatedepletion problems.

As a result, CMOS transistors with metal gates have been attempted.Furthermore, because PMOS and NMOS function differently, it is desirableto fabricate PMOS and NMOS transistors having gates of different workfunctions. Generally, this is obtained by using different metal gates onthe PMOS and NMOS transistors. One method of fabricating PMOS and NMOStransistors is by depositing a first metal layer on both the NMOS andPMOS gates and etching the metal layer from one of them. The etchingprocess, however, frequently damages the gate dielectric layer, therebyaffecting the performance of the transistor.

Another method that has been attempted is to deposit a metal layer forboth the NMOS and PMOS transistors, but then performing an ion implantto alter the work function of either the NMOS or PMOS transistor. Thismethod, however, is difficult to optimize the work function of both theNMOS and PMOS transistors.

Therefore, there is a need for an apparatus, and a method ofmanufacture, with metal gates having a first work function for a PMOSdevice and a second work function for an NMOS device that may befabricated in a cost-effective manner.

SUMMARY OF THE INVENTION

These and other problems are generally reduced, solved or circumvented,and technical advantages are generally achieved, by embodiments of thepresent invention, which provides dual work function gate electrodes.

In one embodiment of the present invention, a semiconductor devicehaving a PMOS transistor and an NMOS transistor with different workfunctions is provided. The gate electrode of the PMOS transistor may beformed by depositing a metal, a metal silicon nitride, a metal compound,a transistion metal, a silicide of a metal or a transition metal, or acombination thereof over a gate dielectric. In the preferred embodiment,tantalum silicon nitride is used. A process, such as annealing, a rapidthermal anneal, a laser treatment, or the like, is performed to form asilicide layer between the gate electrode and the gate dielectric. TheNMOS transistor may be formed by performing a nitridation process on thegate dielectric prior to forming the gate electrode. The gate electrodemay be one or more layers of a conductive material.

In another embodiment of the present invention, a first metal layer isformed over the gate dielectric of a PMOS transistor and an NMOStransistor. A nitridation process is performed on the NMOS transistorand a process, such as annealing, a rapid thermal anneal, a lasertreatment, or the like, is performed to form a silicide layer betweenthe first metal layer and the gate dielectric of the PMOS transistor.The gate electrode is formed over the first metal layer and may be oneor more layers of a conductive material.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1 a-1 f are cross-section views of a wafer illustrating a processof forming dual work function gate electrodes in accordance with a firstembodiment of the present invention; and

FIGS. 2 a-2 d are cross-section views of a wafer illustrating a processof forming dual work function gate electrodes in accordance with asecond embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. In particular, themethod of the present invention is described in the context of formingdual work function gate electrodes of a transistor. One of ordinaryskill in the art, however, will appreciate that the process describedherein may be used for forming any type of device or structure that mayuse dual work function structures. Accordingly, the specific embodimentsdiscussed herein are merely illustrative of specific ways to make anduse the invention, and do not limit the scope of the invention.

Furthermore, the embodiments of the present invention are illustrated asfabricating a PMOS and an NMOS transistor adjacent to each other forillustrative purposes only. The PMOS and NMOS transistors may be spacedapart or fabricated separately. Additionally, other structures, such asisolation trenches may be present.

FIGS. 1 a-1 f illustrate cross-section views of a portion of asemiconductor wafer 100 during various steps of a first methodembodiment of the present invention. The process begins in FIG. 1 a,wherein a semiconductor wafer 100 having a substrate 102 with a firsttransistor 104 and a second transistor 106 formed thereon. Each of thefirst transistor 104 and the second transistor 106 includes a dummy gateelectrode 112, source/drain regions 118, and a dummy gate dielectriclayer 116 formed between the dummy gate electrode 112 and the substrate102. Spacers 120 are formed alongside the dummy gate electrodes 112. Aninterlayer dielectric (ILD) layer 122 may be added to fill the gapsbetween devices, e.g., the first transistor 104 and the secondtransistor 106, and to allow a substantially planar surface. The planarsurface is frequently formed by a chemical mechanical polishing (CMP).The structure shown in FIG. 1 a may be formed by standard processesknown in the art and may comprise either NMOS structures, PMOSstructures, or a combination thereof. The embodiment illustrated inFIGS. 1 a-1 f, however, assume that the first transistor 104 isfabricated as a PMOS transistor and the second transistor 106 isfabricated as an NMOS transistor.

In the preferred embodiment, the spacers 120 are less than about 500 Åin width, the source/drain regions 118 are silicided to a depth of lessthan about 200 Å, and the junction extension depth is less than about200 Å.

In FIG. 1 b, the dummy gate electrode 112 and the dummy gate dielectriclayer 116 are removed. The dummy gate electrode 112 and the dummy gatedielectric layer 116 may be removed, for example, by one or more etchingsteps. In one embodiment of the present invention in which the dummygate electrode 112 comprises polysilicon and the dummy gate dielectric116 comprises silicon dioxide, the dummy gate electrode 112 and dummygate dielectric layer 116 may be removed by for example, a wet or dry,anisotropic or isotropic, etch process, but preferably an anisotropicdry etch process.

It should be noted that in the preferred embodiment a mask (not shown),such as Si₃N₄, a photoresist material, or the like, is applied andpatterned prior to removing the dummy gate electrode 112 and the dummygate dielectric layer 116. The mask protects areas other than the dummygate electrode 112 and the dummy gate dielectric layer 116, such as theILD 122 and spacers 120 during the etching process described above.After removing the dummy gate electrode 112 and the dummy gatedielectric layer 116, the mask may be removed, for example, by using anetch in hot phosphoric acid.

FIG. 1 c illustrates the wafer 100 after a gate dielectric layer 126 isformed. It should be noted that the gate dielectric layer 126 may beformed of the same material as the dummy gate dielectric layer 116 thatwas removed in a previous step. However, the gate dielectric materialmay become damaged during the etching process to remove the dummy gateelectrode. For this reason, it is desirable to remove the dummy gatedielectric layer 116 and reform it as the gate dielectric 126.

In the preferred embodiment, the gate dielectric layer 126 is an oxidelayer formed by any oxidation process, such as wet or dry thermaloxidation in an ambient comprising an oxide, H₂O, NO, or a combinationthereof, or by chemical vapor deposition (CVD) techniques usingtetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor.Alternatively, the gate dielectric layer 126 may be, for example,silicon nitride (Si₃N₄), a material with a dielectric constant greaterthan about 3.9 eV, or the like. In the preferred embodiment, the gatedielectric layer 126 is about 5 Å to about 100 Å in thickness, but morepreferably about 13 Å in thickness. The thickness of the gate dielectriclayer 126 may be thinner or thicker to fulfill specific sizerequirements and electrical characteristics for a particularapplication.

FIG. 1 d illustrates wafer 100 of FIG. 1 c after a mask 130 has beenapplied and patterned, and a portion of the gate dielectric layer 126has become nitrogenated to form a nitride layer 132. Generally, thenitrogenation process comprises introducing nitrogen atoms by exposing asurface to a nitrogen-containing ambient, such as a nitrogen-containingplasma. For gate dielectric layer 126 less than about 40 Å in thickness,it is preferred that the gate dielectric layer 126 is substantiallynitrogenated.

The mask 130 is preferably a photo resist or other polymer that iscommonly used in the art. It should be noted that the mask 130 protectsthe first transistor 104 during the nitridation process. As discussedabove, the first transistor 104 is to be fabricated as a PMOS transistorand the second transistor 106 is to be fabricated as an NMOS transistor.Because it is desirable to only perform the nitridation process on theNMOS transistor, the PMOS transistor is covered with the mask 130.

Nitridation may be performed, for example, by an ion implant, adiffusion process, a laser process, a thermal anneal (e.g., thermalanneal or a rapid thermal anneal (RTA)) in a nitrogen ambient, or by adecoupled plasma nitridation (DPN) process. In this embodiment, thenitridation process forms a nitride layer about 3 Å to about 40 Å inthickness. Other processes and thicknesses may be used.

In FIG. 1 e, the wafer 100 is shown after the mask 130 (FIG. 1 d) hasbeen removed, an electrode layer 134 has been deposited, and the wafer100 has been planarized. The electrode layer 134 may be one or morelayers of any conductive material suitable for the semiconductor devicebeing formed, such as, for example, a metal, a metal compound, atransition metal, metal silicon nitride, a silicide of a transitionmetal or a metal, a combination thereof, or the like. In the preferredembodiment, the electrode layer 134 comprises Si-rich TaSiN and may bedeposited, for example, by sputtering, CVD, atomic layer CVD (ALCVD), orthe like. In another embodiment, a first layer, preferably Si-rich TaSiNor the like, is deposited and a second layer is deposited on the firstlayer. The second layer may be, for example, tantalum, tungsten,aluminum, or the like. The gate electrode is preferably less than about1000 Å.

Preferably, a CMP process is performed after the electrode layer 134 isformed to planarize the surface of the wafer 100. The CMP process may beperformed, for example, utilizing an oxide slurry.

FIG. 1 f illustrates the wafer 100 of FIG. 1 e after an anneal has beenperformed to form a silicide layer 136 between the gate dielectric 126and the gate electrode 134 of the first transistor 104. Annealing causesthe TaSiN to react with the gate dielectric layer 126. In the preferredembodiment in which the gate dielectric layer 126 is formed of silicondioxide, a layer of tantalum silicide (TaSi₂) will be formed between theTaSiN of the gate electrode 134 and the gate dielectric layer 126 of thefirst transistor 104. The TaSi₂ layer generally has a work functionφ_(m) greater than about 4.5 eV, but preferably about 4.8 eV, and aresuitable for use as PMOS devices.

The nitridation performed on the gate dielectric layer 126 of the secondtransistor 106 suppresses the formation of TaSi₂ during the annealingprocess. The TaSiN of the second transistor preferably exhibits a workfunction φ_(m) less than about 4.5 eV, but more preferably about 4.33 eVto about 4.36 eV. It has been found that transistors such as transistor106 are suitable for use as NMOS devices.

FIGS. 2 a-2 d are cross-section views of a portion of a semiconductorwafer 200 during various steps of a second method embodiment of thepresent invention. The second method embodiment illustrated in FIGS. 2a-2 d assumes a wafer similar to the wafer described above withreference to FIGS. 1 a-1 c is provided. Accordingly, the second methodembodiment begins in FIG. 2 a wherein a first electrode layer 210 isformed on a wafer prepared in accordance with wafer 100 of FIGS. 1 a-1c.

The first electrode layer 210 may be any conductive material suitablefor the structure being formed, such as, for example, TaSiN, titanium,nitrides, silicides, metals, transition metals, and the like. In thepreferred embodiment, the first electrode layer 210 comprises Si-richTaSiN and may be deposited, for example, by sputtering.

FIG. 2 b illustrates the wafer of FIG. 2 a after a mask 212 has beenapplied and patterned, and a nitrogenation process has been performed.It should be noted that the mask 212 protects the first transistor 104during the nitrogenation process, which may be performed by a diffusionprocess, an ion implantation process, a laser process, a DPN process, orthe like. A nitride layer 214 is thus formed by the nitrogenationprocess. As discussed above, the first transistor 104 is to befabricated as a PMOS transistor and the second transistor 106 is to befabricated as an NMOS transistor. Because it is desirable to onlyperform the nitrogen implant on the NMOS transistor, the PMOS transistoris protected by the mask 212. The mask 212 is preferably a photo resistor polymer material commonly used in the industry.

In FIG. 2 c, the wafer 200 is shown after the mask 212 has been removedand a silicide layer 216 has been formed. Annealing causes the firstelectrode layer 210 to react with the gate dielectric layer 126, whichis preferably formed of silicon dioxide. In the preferred embodiment inwhich the first electrode layer 210 is TaSiN, a layer of tantalumsilicide (TaSi₂) is formed between the first electrode layer 210 and thegate dielectric layer 126 of the first transistor 104. As discussedabove with reference to FIG. 1 f, the TaSi₂ has a work function ofgreater than about 4.5 eV, which is suitable for PMOS devices.

As a result of the nitrogenation process the gate dielectric layer 126and the first electrode layer 210 may be completely or partiallynitrogenated. The nitridation performed on the gate dielectric layer 126and the first electrode layer 210 of the second transistor 106suppresses the TaSi₂ formation during the annealing process. Asdiscussed above with reference to FIG. 1 f the TaSiN has a work functionof less than about 4.5 eV, which is suitable for NMOS devices.

FIG. 2 d illustrates the wafer 200 after a second electrode layer 218has been formed. The second electrode layer 218 may be one or morelayers of any conductive material suitable for the structure beingformed, such as, for example, a metal, a metal compound, a transitionmetal, metal silicon nitride, a silicide of a transition metal or ametal, a combination thereof, or the like.

Preferably, a CMP process is performed after the second electrode layer218 is formed to planarize the surface of the wafer 200. The CMP processmay be performed, for example, utilizing an oxide slurry.

Thereafter, standard processing steps may be performed to completefabrication of the semiconductor device. For example, an interlayerdielectric (ILD) layer and contacts therethrough may be formed.

In the foregoing specification, the invention has been described withreference to specific embodiments. However, various modifications andchanges can be made by one skilled in the art without departing from thescope of the present invention. Accordingly, the specification andfigures are to be regarded in an illustrative rather than a restrictivesense, and all such modifications are intended to be included within thescope of the present invention. For example, while the present inventionhas been illustrated with reference to fabricating two semiconductordevices, it is understood that the present invention may be extended tofabricate three or more semiconductor devices with structures havingvarying work functions.

Although particular embodiments of the invention have been described indetail, it is understood that the invention is not limitedcorrespondingly in scope, but includes all changes, modifications, andequivalents coming within the spirit and terms of the claims appendedhereto. For example, differing types of materials and differingthicknesses may be used, and the like. Accordingly, it is understoodthat this invention may be extended to other structures and materials,and thus, the specification and figures are to be regarded in anillustrative rather than a restrictive sense.

1. A method of forming a semiconductor device, the method comprising:forming respective gate dielectrics of the first transistor and thesecond transistor; forming a first layer on the gate dielectrics;nitridating the gate dielectric of the second transistor after the stepof forming the first layer; forming respective gate electrodes for thefirst transistor and the second transistor; and after the step ofnitridating, forming a suicide layer by annealing the semiconductordevice, wherein the silicide layer is formed between the gate electrodeof the first transistor and the gate dielectric of the first transistor.2. The method of claim 1, wherein the first transistor is the PMOStransistor and the second transistor is the NMOS transistor.
 3. Themethod of claim 1, wherein the gate dielectric comprises a materialselected from the group consisting of SiO2, SiON, and a combinationthereof.
 4. The method of claim 1, wherein the gate dielectric comprisea material having a dielectric constant greater than about 3.9.
 5. Themethod of claim 1, wherein the gate electrode is formed of a materialselected from the group consisting of a metal, a metal compound, atransition metal, a metal silicon nitride, a silicide of a transitionmetal or a metal, and a combination thereof.
 6. The method of claim 1,wherein the first transistor has a work function greater than or equalto about 4.5 eV.
 7. The method of claim 1, wherein the second transistorhas a work function less than or equal to about 4.5 eV.
 8. The method ofclaim 1, further comprising the step of planarizing the surface of thesemiconductor device.
 9. The method of claim 1, wherein the first layerincludes TaSiN.
 10. The method of claim 1, wherein the step ofperforming the nitridation process is performed by an ion implant, adiffusion process, a laser process, an anneal, or a decoupled plasmanitridation process.
 11. The method of claim 1, wherein the silicidelayer is formed by a process selected from selected from annealing,rapid thermal anneal, and a laser treatment.